Mems nanostructures and methods of forming the same

ABSTRACT

A method of forming of MEMS nanostructures includes a portion of a substrate is recessed to form a plurality of mesas in the substrate. Each of the plurality of mesas has a top surface and a sidewall surface. A light reflecting layer is deposited over the substrate thereby covering the top surface and the sidewall surface of each mesa. A protection layer is formed over the light reflecting layer. An ARC layer is formed over the protection layer. An opening in a photo resist layer is formed over the ARC layer over each mesa. A portion of the ARC layer, the protection layer and the light reflecting layer are removed through the opening to expose the top surface of each mesa. The photo resist layer and the ARC layer over the top surface of each mesa are removed.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims the priority of U.S. ProvisionalApplication No. 61,617,834, filed on Mar. 30, 2012, which isincorporated herein by reference in its entirety.

TECHNICAL FIELD

This disclosure relates to MEMS nanostructures and methods for formingMEMS nanostructures.

BACKGROUND

A fabrication technology of microelectromechanical systems (MEMS)involves forming micro-structures with dimensions in the micrometerscale (one millionth of a meter) in order to implement mechanical,fluidic, optical, biological and/or electrical systems. Significantparts of the fabrication technology have been adopted from integratedcircuit (IC) technology, including cleaning, layering, patterning,etching or doping steps.

MEMS applications include inertial sensors applications, such as motionsensors, accelerometers, and gyroscopes. Other MEMS applications includeoptical applications such as movable mirrors, RF applications such as RFswitches and resonators, and biological sensing structures. Despite theattractive applications noted above, a number of challenges exist inconnection with developing MEMS nanostructures. Various techniquesdirected at configurations and methods of forming these MEMSnanostructures have been implemented to try and further improve deviceperformances.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure may be understood from the followingdetailed description and the accompanying figures. It is emphasizedthat, in accordance with the standard practice in the industry, variousfeatures are not drawn to scale. In fact, the dimensions of the variousfeatures may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1A is a top view of a wafer including a plurality of MEMS chips ona substrate according to one or more embodiments of this disclosure.

FIG. 1B is an enlarged view of a single MEMS chip of FIG. 1A accordingto one or more embodiments of this disclosure.

FIG. 2 is a flowchart of a method of forming a structure of a MEMS chiphaving a MEMS nanostructure according to one or more embodiments of thisdisclosure.

FIGS. 3A and 4 through 9 are cross-sectional views of a structure of theMEMS chip having a MEMS nanostructure at various stages of manufactureaccording to various embodiments of the method of FIG. 2.

FIG. 3B is a top view of the structure of the single MEMS chip of FIG.3A according to one or more embodiments of this disclosure.

FIG. 3C is a perspective view of the single MEMS chip along line A-A′ inFIG. 3B according to one or more embodiments of this disclosure.

FIG. 10 illustrates an enlarged cross-sectional view of a MEMSnanostructure in an operation of detecting biomolecules according to oneor more embodiments.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof the invention. Specific examples of components and arrangements aredescribed below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Moreover,the formation of a first feature over or on a second feature in thedescription that follows may include embodiments in which the first andsecond features are formed in direct contact, and may also includeembodiment in which additional features may be formed interposing thefirst and second features, such that the first and second features maynot be in direct contact. Further still, references to relative termssuch as “top”, “front”, “bottom”, and “back” are used to provide arelative relationship between elements and are not intended to imply anyabsolute direction. Various features may be arbitrarily drawn indifferent scales for simplicity and clarity.

FIG. 1A is a top view of a wafer 100 including a plurality of MEMS chips103 marked on a substrate 102. The plurality of MEMS chips 103 aredivided by scribe lines 106 between the MEMS chips 103. FIG. 1B is anenlarged view of a single MEMS chip 103 depicted in FIG. 1A. Thesubstrate 102 will go through a variety of cleaning, layering,patterning, etching or doping steps to form MEMS nanostructures in theMEMS chips 103. The term “substrate” herein generally refers to a bulksubstrate that is suitable for transmitting electrical or opticalsignals of an analyte. In at least one example, the substrate 102includes a transparent material, such as quartz, sapphire, fused silicaor other suitable glasses. In another example, the substrate is a rigidmaterial which keeps the observed analyte in fixed positions duringobservation. In yet another example, the substrate 102 is a transparentorganic material, for example, methacrylate polymers such as PMMA,polycarbonates, cyclic olefin polymers, styrenic polymers,fluorine-containing polymers, polyesters, polyetherketones,polyethersulfones, polyimides or mixtures thereof. In some embodiments,various layers and devices structures are formed over the substrate 102.Examples of such layers include dielectric layers, doped layers,polysilicon layers or conductive layers. Examples of device structuresinclude transistors, resistors, and/or capacitors, which may beinterconnected through an interconnect layer to additional devices.

FIG. 2 is a flowchart of a method 200 of forming a structure in a MEMSchip having a MEMS nanostructure according to one or more embodiments ofthis disclosure. The method 200 may include forming the MEMSnanostructure using one or more process steps compatible with acomplementary metal-oxide-semiconductor (CMOS) process. The flow chartof the method 200 begins with operation 201 in which a portion of asubstrate is recessed to form a plurality of mesas. Next, the method 200continues with operation 202 in which a light reflecting layer isdeposited over the substrate to cover each mesa. The method 200continues with operation 203 in which a protection layer is formed overthe light reflecting layer. The method 200 continues with operation 204in which an anti-reflective coating (ARC) layer is formed over theprotection layer. The method 200 continues with operation 205 in whichan opening is formed in a photo resist layer over the ARC layer overeach mesa. The method 200 continues with operation 206 in which aportion of the ARC layer, the protection layer and the light reflectinglayer are removed through the opening to expose a top surface of eachmesa. The method 200 continues with operation 207 in which the photoresist layer and the ARC layer over the top surface of each mesa areremoved. It is understood that the method 200 includes steps havingfeatures of a typical CMOS technology process flow and thus, are onlydescribed briefly herein. Further, it is understood that additionalsteps can be provided before, during, and after the method 200. Some ofthe steps described below can be replaced or eliminated for additionalembodiments of the method 200.

FIGS. 3A and 4 through 9 are cross-sectional views of a structure 104 ina MEMS chip having a MEMS nanostructure at various stages of manufactureaccording to various embodiments of the method 200 of FIG. 2. Variousfigures have been simplified for a better understanding of the inventiveconcepts of the present disclosure.

Referring to FIG. 3A, which is an enlarged cross-sectional view of aportion of a structure 104 in a MEMS chip after performing operation201. In FIG. 3A, a portion of a substrate 102 is recessed to form aplurality of mesas 108. The recessed portion of the substrate 102 formsa plurality of recesses 110 surrounding each mesa 108. The adjacentmesas 108 are separated by a recess 110. The recess operation 201 may beformed by using suitable photolithography process to provide a patternon the substrate 102. Then, etching processes are performed to remove aportion of the substrate 102 to define the plurality of mesas 108. Theetching processes may include wet etch, dry etch, plasma etch and/orother suitable processes.

In one embodiment, the mesas 108 are in an arrangement of an array asshown in FIG. 3B with a top view of the structure 104. FIG. 3C is aperspective view of the mesas 108 along line A-A′ in FIG. 3B. FIG. 3A isthe cross-sectional view of the mesas 108 along line A-A′ in FIG. 3B.The substrate 102 has a top surface 102A and a bottom surface 102B. Therecesses 110 extend from the top surface 102A into the substrate 102with a depth D of about 2 μm to 10 μm, while not penetrating through thebottom surface 102B. The recess 110 has an interior surface 110A and abottom surface 110B. The mesa 108 has a top surface and a sidewallsurface adjacent to the top surface. The top surface of the mesa 108 isthe same as the top surface 102A of the substrate 102. The sidewallsurface of the mesa 108 is the same as the interior surface 110A of therecess 110. In one example, the mesa 108 has an interior angle, Angle 1,between a plane parallel to the bottom surface 110B and the interiorsurface 110A, in a range from about 60° to about 85°.

Referring back to FIG. 2, the method 200 continues with operation 202.FIG. 4 illustrates a cross-sectional view of the structure 104 for themanufacture stage after a light reflecting layer 112 is deposited overthe substrate 102 to cover each mesa 108. The light reflecting layer 112covers the top surface 102A, the interior surface 110A and the bottomsurface 110B of each recess 110. In one example, the light reflectinglayer 112 has a thickness in a range from about 1000 Å to about 5000 Å.The mesa 108 and the light reflecting layer 112 disposed on outsidesurfaces (e.g., top surface 102A and interior surface 110A) of the mesa108 is configured as a micro-minor in one example. The light reflectinglayer 112 may enhance the reflectivity of the outside surfaces (102A and110A) of the mesa 108. An operation of the micro-minor will be explainedfurther in the later section as shown in FIG. 10.

The light reflecting layer 112 is an opaque or reflective material. Insome embodiments, the light reflecting layer 112 may be compatible(e.g., friendly) for bio-entity binding. In other embodiments, the lightreflecting layer 112 includes a metallic material such as aluminum,copper, gold, silver, chromium, titanium or mixtures thereof. In thepresent example, the light reflecting layer 112 is an aluminum-copperlayer (also referred to as aluminum-copper layer 112). The lightreflecting layer 112 may be formed by a suitable process, such asphysical vapor deposition (PVD), chemical vapor deposition (CVD) oratomic layer deposition (ALD). In other embodiments, the lightreflecting layer 112 can also comprise a reflective organic polymer,such as a composite material comprising reflective particles dispersedin a polymeric material.

Referring back to FIG. 2, the method 200 continues with operation 203.FIG. 5 illustrates a cross-sectional view of the structure 104 for themanufacture stage after a protection layer 114 is formed over the lightreflecting layer 112 over each mesa 108. In some embodiments, theprotection layer 114 includes oxide layer, nitride layer or othersuitable materials which prevent a metal complex from forming on theunderlying light reflecting layer 112 in the following processes. Insome examples, the protection layer 114 is a conformal liner along a topsurface of the light reflecting layer 112. The protection layer 114 hasa thickness T₁ less than the depth D of the recesses 110.

In the present example, the protection layer 114 is an aluminum oxidelayer. The light reflecting layer 112 (e.g., an aluminum-copper layer)is treated in a plasma environment comprising oxygen to form theprotection layer 114 (e.g., an aluminum oxide layer. The plasmaenvironment comprises a carrier gas such as He, N₂, or Ar. The carriergas helps to control the plasma density and treatment uniformity. In oneembodiment, a flow rate of oxygen is in a range of about 5 standardcubic centimeters per minute (sccm) to about 500 sccm. A flow rate of N₂is in a range of about 10% to about 90% of total gases of the chamberfor the plasma environment. An operation power of the plasma environmentis about 100 W to about 5000 W. An operation pressure of the plasmaenvironment is about 5 mTorr to about 500 mTorr. A thickness T₁ of theprotection layer 114 is in a range from about 10 Å to about 300 Å. Inother examples, the protection layer 114 may be formed by plasmaenhanced chemical vapor deposition (PECVD), high aspect ratio process(HARP) or atomic layer deposition (ALD).

Referring back to FIG. 2, the method 200 continues with operation 204.FIG. 6 illustrates a cross-sectional view of the structure 104 for themanufacture stage after an anti-reflective coating (ARC) layer 116 isformed over the protection layer 114. In some embodiments, the ARC layer116 includes titanium nitride, silicon oxynitride or other suitablematerials which reduce unintended light reflection in the followingphoto resist exposure process. In some examples, the ARC layer 116 is aconformal liner along a top surface of the protection layer 114. In thepresent example, the ARC layer 116 is a titanium nitride layer having athickness T₂ in a range from about 50 Å to about 300 Å. The ARC layer116 may be formed by plasma enhanced chemical vapor deposition (PECVD),high aspect ratio process (HARP) or atomic layer deposition (ALD).

Referring back to FIG. 2, the method 200 continues with operations 205and 206. FIG. 7A illustrates a cross-sectional view of the structure 104for the manufacture stage after an opening 118 is formed in a photoresist layer 120 over the ARC layer 116 for each mesa 108. The photoresist layer 120 is formed over the structure 104 shown in FIG. 6 to alevel above top surfaces of the mesas 108 and the ARC layer 116 bylithography patterning processes. The lithography patterning processesinclude photoresist coating (e.g., spin-on coating), soft baking, maskaligning, exposure, post-exposure baking, developing the photoresist,rinsing, drying (e.g., hard baking) or combinations thereof. Theopenings 118 are formed over the mesas 108 after the lithographypatterning processes. In at least one example, the opening 118 has awidth W in a range from about 110 nm to about 170 nm. Advantageously,the ARC layer 116 beneath the photo resist layer 120 reduces standingwave effects in the photo resist layer 120. The critical dimension (CD)of the width W for the opening 118 could be accurately controlled.

Still referring to FIG. 7A, the patterned photo resist layer 120 is thensubjected to etching process to remove a portion of the ARC layer 116,the protection layer 114 and the light reflecting layer 112 through theopening 118. A portion of the top surface 102A of each mesa 108 isexposed and the opening 118 is also defined within the ARC layer 116,the protection layer 114 and the light reflecting layer 112. In someembodiments, the opening 118 is capable of containing an observedanalyte. The analyte may include an enzyme, an antibody, a ligand, apeptide or an oligonucleotide. In at least one example, the width W ofthe opening 118 is capable of containing only one molecule of theanalyte. The width W contains part of a DNA (deoxyribonucleic acid)strand and polymerase within the opening 118.

FIG. 7B illustrates a cross-sectional view of the structure 104 foranother embodiment in the manufacture stage for forming the opening 118for each mesa 108. Before operations 205 and 206, a filling material 122is filled in the recesses 110 surrounding each mesa 108 and planarizedto a level substantially planar to the top surface 102A of the mesas108. A portion of the ARC layer 116 over the top surface 102A isexposed. Then, the photo resist layer 120 is formed over the exposed ARClayer 116 and the filling material 122. In some examples, the fillingmaterial 122 includes silicon oxide, dielectric material,polycrystalline silicon, amorphous silicon or combinations thereof. Thefilling material 122 is formed by low temperature chemical vapordeposition (LTCVD) at an operation temperature less than 300° C. toprevent damaging the substrate 102 for electrical or optical signalsdetection. Advantageously, the planarized filling material 122 and theARC layer 116 over the surface 102A form a smooth surface. The smoothsurface enhances the capability to achieve a better resolution of thefollowing lithography process on the smooth surface.

Referring back to FIG. 2, the method 200 continues with operation 207which is illustrated in FIGS. 8 and 9. In FIG. 8, the photo resist layer120 is removed from the structure 104. In some examples, the photoresist layer 120 is ashed in a plasma environment comprising oxygen. Inother examples, the photo resist layer 120 is stripped in wet chemicalsolutions.

In FIG. 9, the ARC layer 116 is removed from the structure 104. In someexamples, wet chemical solutions are used to selectively remove the ARClayer 116 and without substantially etch the underlying protection layer114. In the present example, the ARC layer 116 is a titanium nitridelayer. The titanium nitride layer is removed in a wet solutioncomprising H₂O₂. In one embodiment, a flow rate of H₂O₂ is in a range ofabout 10 standard cubic centimeters per minute (sccm) to about 500 sccm.An operation temperature is in a range of about 40 to about 70° C. Inone example shown in FIG. 7A, the entire ARC layer 116 over each mesa108 is removed and the protection layer 114 is exposed. In anotherexample shown in FIG. 7B, the exposed ARC layer 116 over the fillingmaterial 122 is removed. Other portion of the ARC layer 116 is embeddedin the filling material 122. Advantageously, the protection layer 114protects the underlying layers during the ARC layer 116 removal andprevents damaging the light reflecting layer 112 and the substrate 102for electrical or optical signals detection. Additionally, theprotection layer 114 is formed between the ARC layer 116 and the lightreflecting layer 112. The protection layer 114 prevents any residual ofthe ARC layer 116 from forming a metal complex with the underlying lightreflecting layer 112. In the operation of detecting biomolecules, theobserved analyte is free of interfering by the metal complex.

After the operation 207, a MEMS nanostructure 124 having a micro-mirroris formed in the structure 104 of MEMS chip.

In some embodiments, further process steps are optionally included afterthe operation 207. In some embodiments, a mechanically sawing or a lasersawing is performed along the scribe lines 106 of the wafer 100 and thesubstrate 102 are sawed into individual MEMS chips 103.

FIG. 10 illustrates an enlarged cross-sectional view of a MEMSnanostructure 124 in an operation of detecting biomolecules. The MEMSnanostructure 124 includes a mesa 108 integrally connected a portion ofa substrate 102. The mesa 108 has the top surface corresponding to thetop surface 102A of the substrate 102 and the sidewall surface adjacentto the top surface and corresponding to sidewall surface 110A of recess110. A light reflecting layer 112 is disposed over the top surface 102Aand the sidewall surface 110A. The mesa 108 and the light reflectinglayer 112 disposed on the outside surfaces (102A and 110A) of the mesa108 is configured as a micro-minor. A protection layer 114 is disposedover the light reflecting layer 112. An opening is disposed in theprotection layer 114 and the light reflecting layer 112 to partiallyexpose the portion of the top surface 102A of the substrate 102. Duringthe detecting operation as a biological sensor, an analyte 126 isdisposed in the opening of the MEMS nanostructure 124. The analyte 126may include an enzyme, an antibody, a ligand, a peptide or anoligonucleotide. A source of excitation radiation (not shown) generatesradiation incident on the analyte 126. The analyte 126 may emit a lightoutput 128 to the underneath micro-minor. The micro-mirror reflects thelight output 128 and conveys the light output 128 to a detector 130below the bottom surface 102B of substrate 102. The detector 130collects the light output 128 and stores the light output 128 in astorage apparatus for analysis. The light reflecting layer 112 mayenhance the reflectivity of the outside surfaces (102A and 110A) of themesa 108.

One aspect of the disclosure describes a method of forming a pluralityof MEMS nanostructures. A portion of a substrate is recessed to form aplurality of mesas in the substrate. Each of the plurality of mesas hasa top surface and a sidewall surface adjacent to the top surface. Alight reflecting layer is deposited over the substrate thereby coveringthe top surface and the sidewall surface of each mesa. A protectionlayer is formed over the light reflecting layer. An ARC layer is formedover the protection layer. An opening in a photo resist layer is formedover the ARC layer over each mesa. A portion of the ARC layer, theprotection layer and the light reflecting layer are removed through theopening to expose the top surface of each mesa. The photo resist layerand the ARC layer over the top surface of each mesa are removed.

A further aspect of the disclosure describes a method of forming aplurality of MEMS nanostructures. A portion of a substrate is recessedto form a plurality of mesas in the substrate. Each of the plurality ofmesas has a top surface and a sidewall surface adjacent to the topsurface. A light reflecting layer is deposited over the substratethereby covering the top surface and the sidewall surface of each mesa.A protection layer is conformally formed along the light reflectinglayer. An ARC layer is formed over the protection layer. An opening in aphoto resist layer is formed over the ARC layer over each mesa. Aportion of the ARC layer, the protection layer and the light reflectinglayer are removed through the opening to expose the top surface of eachmesa. The photo resist layer and the ARC layer are removed withoutsubstantially removing the protection layer.

Another aspect of the disclosure describes a method of forming aplurality of MEMS nanostructures. A portion of a substrate is recessedto form a plurality of mesas in the substrate. Each of the plurality ofmesas has a top surface and a sidewall surface adjacent to the topsurface. A light reflecting layer is deposited over the substratethereby covering the top surface and the sidewall surface of each mesa.A protection layer is formed over the light reflecting layer. An ARClayer is formed over the protection layer. A filling material is formedsurrounding each mesa to expose a portion of the ARC layer. An openingin a photo resist layer is formed over the exposed ARC layer over eachmesa. A portion of the exposed ARC layer, the protection layer and thelight reflecting layer are removed through the opening to expose the topsurface of each mesa. The photo resist layer and the exposed portion ofthe ARC layer are removed.

Although the embodiments and its advantages have been described indetail, it should be understood that various changes, substitutions andalterations can be made herein without departing from the spirit andscope of the invention as defined by the appended claims. Moreover, thescope of the present application is not intended to be limited to theparticular embodiments of the process, machine, manufacture, andcomposition of matter, means, methods and steps described in thespecification. As one of ordinary skill in the art will readilyappreciate from the disclosure of the present invention, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein may be utilized according tothe present invention. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, methods, or steps.

What is claimed:
 1. A method of forming a plurality of MEMSnanostructures, the method comprising: recessing a portion of asubstrate to form a plurality of mesas in the substrate, wherein each ofthe plurality of mesas has a top surface and a sidewall surface adjacentto the top surface; depositing a light reflecting layer over thesubstrate thereby covering the top surface and the sidewall surface ofeach mesa; forming a protection layer over the light reflecting layer;forming an anti-reflective coating (ARC) layer over the protectionlayer; forming an opening in a photo resist layer over the ARC layerover each mesa; removing a portion of the ARC layer, the protectionlayer and the light reflecting layer through the opening to expose thetop of each mesa; and removing the photo resist layer and the ARC layerover the top surface of each mesa.
 2. The method of claim 1, wherein thelight reflecting layer comprises aluminum, copper, gold, silver,chromium, titanium or mixtures thereof.
 3. The method of claim 1,wherein the protection layer comprises oxide layer or nitride layer. 4.The method of claim 1, wherein forming the protection layer comprisestreating the light reflecting layer in a plasma environment comprisingoxygen.
 5. The method of claim 1, wherein the opening has a widthcapable of containing only one molecule of an analyte.
 6. The method ofclaim 1, wherein the opening has a width in a range from about 110 nm toabout 170 nm.
 7. The method of claim 1 further comprising forming afilling material surrounding each mesa before the step of forming theopening in the photo resist layer.
 8. The method of claim 7 furthercomprising planarizing the filling material to a level substantiallyplanar to the top surface of each mesa.
 9. The method of claim 1,wherein removing the ARC layer comprises removing in a wet solutioncomprising H₂O₂.
 10. The method of claim 1, wherein removing the ARCcomprises removing an entire ARC layer over each mesa.
 11. A method offorming a plurality of MEMS nanostructures, the method comprising:etching a portion of a substrate to form a plurality of mesas in thesubstrate, wherein each of the plurality of mesas has a top surface anda sidewall surface adjacent to the top surface; depositing a lightreflecting layer over the substrate thereby covering the top surface andthe sidewall surface of each mesa; forming a protection layerconformally along the light reflecting layer; forming an anti-reflectivecoating (ARC) layer over the protection layer; forming an opening in aphoto resist layer over the ARC layer over each mesa; removing a portionof the ARC layer, the protection layer and the light reflecting layerthrough the opening to expose the top of each mesa; and removing thephoto resist layer and the ARC layer without substantially removing theprotection layer.
 12. The method of claim 11, the light reflecting layercomprises aluminum, copper, gold, silver, chromium, titanium or mixturesthereof.
 13. The method of claim 11, wherein the protection layercomprises oxide layer or nitride layer.
 14. The method of claim 13,wherein the protection layer is an aluminum oxide layer in a thicknessrange of about 10 Å to about 300 Å.
 15. The method of claim 11, whereinthe opening has a width capable of containing only one molecule of ananalyte.
 16. The method of claim 11, removing the ARC layer comprisesremoving in a wet solution comprising H₂O₂.
 17. A method of forming aplurality of MEMS nanostructures, the method comprising: recessing aportion of a substrate to form a plurality of mesas in the substrate,wherein each of the plurality of mesas has a top surface and a sidewallsurface adjacent to the top surface; depositing a light reflecting layerover the substrate thereby covering the top surface and the sidewallsurface of each mesa; forming a protection layer over the lightreflecting layer; forming an anti-reflective coating (ARC) layer overthe protection layer; forming a filling material surrounding each mesato expose a portion of the ARC layer; forming an opening in a photoresist layer over the exposed ARC layer over each mesa; removing aportion of the exposed ARC layer, the protection layer and the lightreflecting layer through the opening to expose the top of each mesa; andremoving the photo resist layer and the exposed portion of the ARC layerof each mesa.
 18. The method of claim 17, the light reflecting layercomprises aluminum, copper, gold, silver, chromium, titanium or mixturesthereof.
 19. The method of claim 17, wherein forming the protectionlayer comprises treating the light reflecting layer in a plasmaenvironment comprising oxygen.
 20. The method of claim 17, the fillingmaterial comprises silicon oxide, dielectric material, polycrystallinesilicon, amorphous silicon or combinations thereof.